1. Field of the Invention
The present invention relates to oscillator circuits, and particularly to oscillator circuits that may be enabled and disabled.
2. Description of the Related Art
Clock generation circuits generally use either a quartz crystal or an oscillator as a clock source. A quartz crystal is a passive, 2-pin component that requires a driver circuit to excite the crystal into resonance, and a receiver circuit to amplify the signal generated by the piezoelectric effect within the crystal, and to generate a useful clock signal. The driver and receiver circuits are frequently embedded within a controller circuit, such as a microprocessor, microcontroller, digital signal processor, network controller circuit, or virtually any digital circuit that utilizes a clock signal. When implemented in this manner, only the crystal is external to the controller circuit, and the remainder of the clock generator circuit is formed within the controller circuit.
Referring to FIG. 1, a clock generator 100 is depicted which utilizes a traditional crystal oscillator circuit. A controller circuit 102 includes a driver circuit 104 for driving a crystal output (i.e., XTAL_OUT) terminal 105, and further includes a receiver circuit 110 responsive to a crystal input (i.e., XTAL_IN) terminal 109. External to the controller circuit 102, a crystal 112 is connected between the XTAL_OUT terminal 105 and the XTAL_IN terminal 109. Such a crystal 112 may be incorporated within the package of the controller circuit 102, or may be located on a printed wiring board (PWB) adjacent to the controller circuit 102. One terminal 106 of the crystal 112 is connected to the XTAL_OUT terminal 105, and the other terminal 108 of the crystal 112 is connected to the XTAL_IN terminal 109.
Within the controller circuit 102, an inverting gain element 114 is provided to close the loop incorporating the crystal 112 and sustain oscillation of the circuit. The inverting gain element 114 may be, in some embodiments, as simple as a digital inverter whose input and output terminals are biased nominally at a mid-rail voltage, such as by a resistor (not shown) coupling the input of the inverter 114 to the output of the inverter 114. Of note, the signal level generated on the XTAL_OUT terminal 105 by the driver 104 is typically a low-amplitude signal, as it needs merely to excite the crystal to resonate. Also provided within the controller circuit 102 is additional buffering, such as is represented by buffer 116, to amplify the output of receiver 110 and generate an internal clock signal on node 118 with a drive strength appropriate for the internal load within the controller circuit 102. If the controller circuit 102 desires to disable the oscillator circuit, such as for a low power mode of operation, the driver circuit 104 may be disabled, thus breaking the feedback loop and preventing oscillations on XTAL_IN node 109.
An oscillator circuit (i.e., sometimes described as a “stand-alone” oscillator circuit) is typically an active, 4-pin component that requires connection to power and ground, and has a digital enable input, and a digital clock output. Referring now to FIG. 2, a clock generator 150 is depicted utilizing a traditional oscillator circuit 162. A controller circuit 152 includes a driver circuit 154 for driving a digital clock enable output signal (i.e., CLKEN) onto output terminal 156, and further includes a receiver circuit 160 responsive to a digital clock input signal (i.e., CLK_IN) conveyed on input terminal 158. External to the controller circuit 152, an oscillator circuit 162 is coupled to a power supply voltage VDD conveyed on node 164, and further coupled to ground reference voltage (i.e., GND) conveyed on node 166. Both the VDD and GND connections are usually provided directly by a printed wiring board upon which the oscillator circuit 162 is typically mounted. The oscillator circuit 162 has an enable input EN connected to node 156 to receive the CLKEN signal from the controller circuit 152, and further has a clock output CLK_OUT connected to node 158 to provide the clock signal to the controller circuit 152.
Within the controller circuit 152, the receiver circuit 160 is included to generate an internal clock signal on node 118 with drive strength appropriate for the internal load within the controller circuit 152. The receiver circuit 160 may include multiple stages of buffering, as dictated by considerations within the controller circuit 152. Of note, the signal level generated on the CLKEN output terminal 156 is typically a full-rail digital signal, as is typical for digital control signals. If the controller circuit 152 desires to disable the oscillator circuit 162, such as for a low power mode of operation, the driver circuit 154 is driven to generate an inactive level on the CLKEN signal (i.e., to de-assert the enable signal), which disables the generation of the CLK_OUT signal by the oscillator 162 and may also put the oscillator into a low power state.